MA320002【PDF 37/208 页】MODULE PLUG-IN PIC32 USB OTG

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PIC32MX3XX/4XX

TABLE 3-1:

PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU

MUL

DIV/DIVU

Operand Size (mul rt ) (div rs )

16 bits

32 bits

16 bits

32 bits

8 bits

16 bits

24 bits

32 bits

Latency

1

2

2

3

12

19

26

33

Repeat Rate

1

2

1

2

11

18

25

32

The MIPS architecture defines that the result of a mul-

tiply or divide operation be placed in the HI and LO reg-

isters. Using the Move-From-HI ( MFHI ) and Move-

From-LO ( MFLO ) instructions, these values can be

transferred to the general purpose register file.

the product to the current contents of the HI and LO

registers. Similarly, the MSUB instruction multiplies two

operands and then subtracts the product from the HI

and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

In addition to the HI/LO targeted operations, the

MIPS32 architecture also defines a multiply instruction,

MUL, which places the least significant results in the

3.2.3

SYSTEM CONTROL

COPROCESSOR (CP0)

primary register file instead of the HI/LO register pair.

By avoiding the explicit MFLO instruction, required

when using the LO register, and by supporting multiple

destination registers, the throughput of

multiply-intensive operations is increased.

Two other instructions, multiply-add ( MADD ) and multi-

ply-subtract ( MSUB ), are used to perform the multiply-

accumulate and multiply-subtract operations. The

MADD instruction multiplies two numbers and then adds

In the MIPS architecture, CP0 is responsible for the vir-

tual-to-physical address translation, the exception con-

trol system, the processor ’s diagnostics capability, the

operating modes (kernel, user and debug), and

whether interrupts are enabled or disabled. Configura-

tion information, such as presence of options like

MIPS16e, is also available by accessing the CP0

registers, listed in Table 3-2.

TABLE 3-2:

COPROCESSOR 0 REGISTERS

Register Register

Number Name

Function

0-6

7

8

9

10

11

12

12

12

12

13

14

15

15

16

16

16

16

Reserved

HWREna

BadVAddr (1)

Count (1)

Reserved

Compare (1)

Status (1)

IntCtl (1)

SRSCtl (1)

SRSMap (1)

Cause (1)

EPC (1)

PRId

EBASE

Config

Config1

Config2

Config3

Reserved in the PIC32MX3XX/4XX Family core

Enables access via the RDHWR instruction to selected hardware registers

Reports the address for the most recent address-related exception

Processor cycle count

Reserved in the PIC32MX3XX/4XX Family core

Timer interrupt control

Processor status and control

Interrupt system status and control

Shadow register set status and control

Provides mapping from vectored interrupt to a shadow set

Cause of last general exception

Program counter at last exception

Processor identification and revision

Exception vector base register

Configuration register

Configuration register 1

Configuration register 2

Configuration register 3

? 2010 Microchip Technology Inc.

DS61143G-page 37

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